(Dr. Daniel Baldwin, advisor)
"Flip Chip Packaging Using High Melting Point Solder Interconnect Systems and the High Throughput Flip Chip Process"
Flip Chip on Board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. Current assembly processes are not capable of providing the high throughputs needed for integrated Surface Mount Technology (SMT) processing. A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process as necessary for FCOB assemblies.
The goal of this research was to integrate the high throughput flip
chip process on commercial flip chip packages and to assess underfill compatibility
with different substrate designs. The first part focused on application
of no-flow underfills with a commercial package utilizing the classical
high lead on eutectic solder interconnects. This involved extensive
experimentation into underfill promotion of solder wetting and package
void minimization to provide acceptable component performance and reliability.
The second part focused on analysis of substrate features and their effects
on void capture in no-flow underfills using the high throughput flip chip
process. This involved a thorough statistical analysis of main and
interaction effects among a selection of factors, and provided significant
knowledge on appropriate substrate design and assembly process specifications
that minimize underfill void capture. In essence, the research helped
expand the applicability of the high throughput process into the commercial
packaging arena, and provided insight into appropriate solder wetting and
underfill voiding relative to controllable design and processing factors.