(Dr. Daniel Baldwin, advisor)
"Evaluation and Process Development of Wafer-Level-Applied Underfill Material Systems for Flip Chip Assembly"
As integrated circuits continue to evolve, the limitations of existing electronic packaging, such as SMT (surface mount technology), are becoming more evident. Flip chip packaging, in which the active face of the bare silicon die is placed face down on the substrate, is characterized by higher I/O densities, shorter signal paths, and smaller area requirements as compared to typical SMT components. When implemented in electronic components, flip chip packaging results in higher performance, reduced size and weight, and lower material costs associated with packaging. In order to utilize flip chips on low cost, organic substrates, an underfill is typically used to mechanically couple the chip to the board, reinforcing the interconnects which are subjected to high thermo-mechanical stress. Currently, underfill application requires several additional process steps for electronics manufacturers, which has limited the use of flip chips in industry. However, by applying underfill at the wafer level, certain process steps and associated costs are eliminated, and flip chip packaging can potentially become more widely used.
This thesis includes the evaluation and process development of underfill material systems suitable for wafer-level usage. The primary focus of this thesis is on the process development and characterization of the initial stages of the wafer-level flip chip assembly process. Underfill liquification, fillet formation, and package collapse are investigated in detail. Process experiments are conducted to determine the effect of underfill coating uniformity on assembly quality, as well as to consider the effect of patterns in the solder mask of the substrate with respect to die alignment. Observations of the physical phenomena driving fillet formation and package collapse are made with a video imaging system. In addition, predictive models are developed to determine the theoretical die misalignment for various situations. The goal of this research is to develop a better understanding of the wafer-level flip chip assembly process.